1. Field of the Invention
The present invention relates to a semiconductor device such as a power device which has a guard ring structure.
2. Description of the Background Art
As a conventional method for improving the surge endurance, there are several propositions such as those disclosed in Japanese Patent Application Laid Open No. 60-196975 (1985) and Japanese Patent Application Laid Open No. 61-182264.
An example from the latter reference is shown in FIG. 1, where a device comprises an N+ substrate 101, an epitaxial layer 102, a guard ring 103, a channel region 104, a source region 105, a gate oxide 106, a gate electrode 107, field oxide 108, a source electrode 109, and a drain electrode 110.
In this conventional example, in order to prevent the avalanche failure due to the surge occurring at a time of switching the induction load by using a power MOS, there is provided a diffusion profile in which a bottom of the channel region 104 of a MOSFET cell is reaching an N+ substrate 101 such that the breakdown voltage of this portion is lowered, so as to provide a function of a Zener diode.
Also, in this conventional example, the surge endurance is improved as an effective Zener area is increased by applying the same structure to a guard ring 103 surrounding the channel region 104.
Next, another conventional example for improving the surge endurance is shown in FIG. 2, where those elements equivalent to the corresponding ones in the prior example are given the same reference numerals, and where there is also provided a well region 111 for forming a Zener. In this conventional example, the guard ring 113 is formed in the same diffusion profile as the well region 111, and the channel region 104 and the well region 111 are separately provided so as to be able to reduce the variations in manufacturing by optimally controlling each region separately.
Now, in recent years, there has been a very noticeable trend in the field of power MOS to compactify the FET cell by using the ultra fine manufacturing technique. This is due to the feature of the power MOS that by manufacturing a finer cell, the packing density can be increased and the on-resistance can be reduced.
However, in a conventional semiconductor device such as those shown in FIGS. 1 and 2, the finer cell has often resulted in creating a situation in which the breakdown voltage of the cell unit exceeds that of the guard ring, in which case the surge current mainly flows through the guard ring, such that the surge endurance of the chip as a whole is lowered.
According to the research done by the present inventors in order to understand the aforementioned problem, this problem is caused by the fact that the lower concentration of the diffusion profile occurring in the case where the diffusion window size S of the Zener cell is smaller than twice the diffusion depth Xj of the Zener cell, compared with the other cases.
Namely, as shown in FIG. 3, when the diffusion takes place simultaneously from a window W1 of an opening sufficiently larger than its diffusion depth Xj1 and from a window W2 of an opening smaller than a twice of its diffusion depth Xj2, the window W2 receives more influence from the two dimensional spread effect compared with the window W1, so that the impurity concentration at the central portion X2--X2 of the window W2 becomes lower than that at the central portion X1-X1 of the window W1, and the diffusion depth becomes shallower for the window W2.
For instance, the diffusion profile for the device of FIG. 1 described above, with a cell opening S=3 .mu.m, a guard ring width W=30 .mu.m, and the diffusion depth=approximately 4 .mu.m, is shown in FIG. 4.
As shown in FIG. 4, the impurity concentration for the cell unit indicated by a curve B-Bp, which was measured along B--B section of the channel region 104 in FIG. 1, is lower than one third of that of the guard ring indicated by a curve A-Ap, which was measured along A-A section of the guard ring 103 in FIG. 1. In this case, the breakdown voltage for the cell unit is equal to 37 V while that of the guard ring is equal to 35 V, and the evidence of all the current to concentrate to the guard ring alone had been found in the surge application test.
The impurity concentrations for the cell unit and the guard ring measured along B-B section and A-A section, respectively, in FIG. 2 also have the similar forms as shown in FIG. 4. Therefore, the similar result can also be observed for the device of FIG. 2 described above, in which this situation occurs when the diffusion window of well region 111 is smaller than a twice of its diffusion depth.